In recent years, development of miniaturization technique to achieve miniaturization and high densification is required along with high integration and high functionality of a semiconductor integrated circuit device. Particularly, importance of a planarization technique by chemical mechanical polishing (hereinafter referred to as CMP) has been increasing.
For example, along with miniaturization and multilayered structures of wiring of a semiconductor integrated circuit device, unevenness on the surface of each layer in production steps tends to be significant. In order to prevent such problems that the unevenness exceeds the depth of focus of photolithography, whereby no sufficient resolution will be obtained, CMP is an essential technique. CMP is employed, specifically, for planarization of an interlevel dielectric (ILD) film, shallow trench isolation (STI), tungsten plug formation, formation of multilayered wiring comprising copper and a low dielectric film, etc. In such cases, a polysilicon film is used for a capacitor, a gate electrode, etc. in many cases, and CMP is employed also for planarization of a plane to be polished including the polysilicon film.
Heretofore, in production of a semiconductor integrated circuit device, when the plane to be polished including a polysilicon film is planarized, usually, a silicon dioxide film or a silicon nitride film as a stopper layer is formed as an underlayer of the polysilicon film to be polished, and the ratio of the polishing rate of the polysilicon film to the polishing rate of the silicon dioxide film or the silicon nitride film (hereinafter (polishing rate of A)/(polishing rate of B) will sometimes be referred to as a “polishing rate ratio of A to B”) is adjusted to be high, so that the plane to be polished is planarized upon exposure of the stopper layer.
For planarization of the plane to be polished including a polysilicon film, a SS series polishing compound containing fumed silica, water and potassium hydroxide manufactured by Cabot Corporation, has been used. However, this polishing compound is used also for polishing a silicon dioxide film for planarization of ILD, and accordingly when it is used for planarization of a plane to be polished with the stopper layer being a silicon dioxide film, the polishing rate of the silicon dioxide film is high, whereby the polishing rate ratio of the polysilicon film to the silicon dioxide film tends to be low. Further, with this polishing compound, the polishing rate ratio of the polysilicon film to a silicon nitride film is also low, and use of this polishing compound for planarization of a plane to be polished including a polysilicon film with the stopper layer being a silicon nitride film, is problematic.
To solve the above problems, Patent Document 1 proposes a polishing composition comprising at least one type of abrasive particles selected from fumed silica and colloidal silica as a polishing compound and an amine as a basic compound, as a polishing composition suitable for planarization of a plane to be polished including a polysilicon film. The polishing composition disclosed in this Patent Document is considered to be a polishing compound suitable for planarization of a plane to be polished including a polysilicon film, since when a silicon dioxide film is used as the stopper layer, the polishing rate ratio of a polysilicon film to a silicon dioxide film is high. Further, with this polishing composition, the polishing rate ratio of a polysilicon film to a silicon nitride film is also high, and this polishing composition is considered to make it possible to planarize a plane to be polished with the stopper layer being a silicon nitride film.
However, a polishing compound having such properties is unsuitable for planarization of a plane to be polished including a polysilicon film to be used for a capacitor, a gate electrode, etc. in formation of multilayered wiring, wherein a silicon nitride film is used as the stopper layer, and a polysilicon film and a silicon dioxide film on the silicon nitride film are to be polished. Namely, since the polishing rate of the silicon dioxide film is low as compared with the polishing rate of the polysilicon film, removal of the silicon dioxide film by polishing before the polishing compound reaches the silicon nitride film as the stopper layer will not sufficiently be conducted. In such a layer structure, it is required that the polishing rate of a silicon dioxide film is sufficiently high so as to be equal to the polishing rate of the polysilicon film and that the polishing rate of the silicon nitride film is sufficiently small as compared with the polishing rate of the polysilicon film, but the polishing compound having the above properties can not meet such requirements.
Patent Document 1: Japanese Patent No. 3457144
Patent Document 2: JP-A-11-12561
Patent Document 3: JP-A-2001-35818